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| R80515 8-bit Microcontroller Megafunction General Description The R80515 is a fast, single-chip, 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of 8 times faster. The R80515 provides software and hardware interrupts, extra timer features, power management, and Infinion peripherals support. On-chip debugging is an option. The microcode-free, strictly synchronous design was developed for reuse in ASICs and FPGAs. Features * * * * * * * * * * * * * * Single clock per machine cycle Reduced instruction cycle time up to 12 times 8-bit Control Unit 8-bit Arithmetic-Logic Unit Multiplication/Division Unit o 16 x 16-bit multiplication and division; 32 / 16-bit division Four 8-bit Input/Output ports Alternate port functions such as external interrupts & serial interface are separated, providing extra port pins when compared with the standard 8051 Three 16-bit Timer/Counters Compare/Capture Unit Two Serial Peripheral Interfaces in full duplex mode Four priority/thirteen sources Interrupt Controller 15-bit Programmable Watchdog Timer Internal Data Memory interface can address up to 256 bytes of Read/Write Data Memory Space External o o o o o o Memory interface Can address up to 64 K bytes of External Program Memory Space Can address up to 64K bytes of External Data Memory Space De-multiplexed address/data bus to allow easy connection to memories Variable length MOVX to access fast/slow RAM or peripherals Variable length code fetch and MOVC to access fast/slow program memory Dual data pointer for fast data block transfers * * * Special Function Registers interface: serves up to 74 external registers Power Management Unit Optional JTAG debugging March 2004 Page 1 CAST, Inc. R80515 Megafunction Datasheet Applications Pin Description Name port0i port0o port1i port1o Type In Out In Out Polarity/ Bus Size 8 8 8 8 Description Port 0 8-bit bi-directional I/O port with separated inputs and outputs Port 1 8-bit bi-directional I/O port with separated inputs and outputs Port 2 8-bit bi-directional I/O port with separated inputs and outputs Port 3 8-bit bi-directional I/O port with separated inputs and outputs Clock A pulse for internal clock counters and all synchronous circuits Hardware reset Resets the device when this pin is held high for two clock cycles while the oscillator is running Engine clock A pulse for internal circuits that are stopped when the R80515 is in the IDLE or STOP mode Engine clock output Is the gated clk clock. clkcpuo stays low when the R80515 enters into IDLE or STOP mode. The clkcpuo is dedicated to off-core connection to the clkcpu input Peripheral clock A pulse for internal circuits that are stopped when the R80515 is in STOP mode Peripheral clock output is the gated clk clock. clkpero stays low when the R80515 enters into STOP mode. The clkpero is dedicated to off-core connection to the clkper input Page 2 * * * * Embedded microcontroller systems Data computation and transfer Communication systems Professional audio and video Symbol reset clk port2i port2o In Out 8 8 R80515 clkcpu clkcpuo clkper clkpero swd port0i port1i port2i port3i port0o port1o port2o port3o ramdatai ramdatao ramaddr ramwe ramoe port3i port3o clk In Out In 8 8 Rising reset In High int0 int1 int2 int3 int4 int5 int6 cc0 cc1 cc2 cc3 t0 t1 t2 t2ex rxd0i rxd0o txd0 rxd1i clkcpu In Rising sfrdatai sfrdatao sfraddr sfrwe sfroe memdatai memdatao memaddr mempswr mempsrd memwr memrd clkcpuo Out Rising clkper In Rising clkpero o Out Rising txd1 CAST, Inc. R80515 Megafunction Datasheet Name swd Type In Polarity/ Bus Size High Description Start Watchdog Timer A high on this pin during reset starts the watchdog timer immediately after reset is released External Interrupts External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Compare/Capture Compare/Capture 0 Compare/Capture 1 Compare/Capture 2 Compare/Capture 3 Serial 0 interface Serial 0 receive data Serial 0 transmit data Serial 0 transmit data or receive clock in mode 0 Serial 1 interface Serial 1 receive data Serial 1 transmit data Timer inputs Timer 0 external input Timer 1 external input Timer 2 external input Timer 2 capture trigger External Memory interface Memory data input Memory data output Memory address Program store write enable Program store read enable Data Memory write enable Data Memory read enable Internal Data Memory interface Data bus input Data bus output Data file address Data file write enable Data file output enable Name Type Polarity/ Bus Size Description External Special Function Registers interface SFR data bus input SFR data bus output SFR address SFR write enable SFR output enable sfrdatai sfrdatao sfraddr sfrwe sfroe I O O O O 8 8 7 High High into int1 int2 int3 int4 int5 int6 cco cc1 cc2 cc3 rxd0i rxd0o txd0 In In In In In In In In In In In In Out Out Low/Falling Low/Falling Fall./Rising Fall./Rising Rising Rising Rising High High High High - rxd1i rxd1o t0 t1 t2 t2ex In Out In In In In Falling Falling Falling Falling memdatai memdatao memaddr mempswr mempsrd memwr memrd In Out Out Out Out Out Out 8 8 16 High High High High ramdatai ramdatao ramaddr ramwe ramoe In Out Out Out Out 8 8 8 High High CAST, Inc. Page 3 R80515 Megafunction Datasheet Block Diagram memdatai memdatao memaddr mempsack mempsrd mempswr memack memwr memrd MEMORY_CONTROL pc dptr dptr1 TIMER_0_1 tl0 tl1 tf0, ie0 ISR ie0 ie1 ie2 com0,1,2,3 TIMER_2 tl2 crcl ccl1 ccl2 ccl3 internal sfrbus th2 crch cch1 cch2 cch3 ip0 ip1 ircon th0 th1 tcon tmod tf1, ie1 t0 t1 int0 int1 int2 int3 int4 int5 int6 t2 t2ex cc0 cc1 cc2 cc3 fetch instr cycle CONTROL_UNIT instrreg fetch ramdatai ramdatao ramaddr ramoe ramwe sfrdatai sfrdatao sfraddr sfroe sfrwe sp instr cycle tf2, exf2 t2con 4x CCU_PORT RAM_SFR_CONTROL ccu_bus PORTS p0 p1 p2 p3 port1i port2i port3i port0 port1o port2o port3o swd clk clkcpu clkcpuo clkper clkpero reset instr ALU acc rxd0i rxd0o txd0 rxd1i txd1 b cycle psw WATCHDOG_TIMER wdtrel PMU SERIAL_0 s0rell s0relh SERIAL_1 s1rell s1relh MDU s0con s0buf s1con s1buf RSTCTRL md0 md2 md4 arcon md1 md3 md5 CLOCK_CONTROL pcon ckcon CAST, Inc. Page 4 R80515 Megafunction Datasheet Verification Methods The R80515 core's functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C31 and Siemens SAB80C537 chips, and the results were compared with the core's simulation outputs. Device Utilization & Performance Supported Family Cyclone Stratix Stratix-II Notes: 1. Device Tested EP1C4-6 EP1S10-5 EP2S5-3 LEs 3696 3726 3115 Utilization Memory Memory bits 3 M4K 10,240 3 M4K 10,752 3 M4K 10,752 Performance Fmax 38 MHz 39 MHz 51 MHz 2. Optimized for speed Implemented with 256 bytes of RAM and 1KB of ROM Deliverables * * * * * * * * VHDL or Verilog HDL source code Post-synthesis EDIF netlist (netlist license) Testbench (self-checking) Vectors for testing the core Place & route scripts (netlist license) Simulation script Synthesis script Documentation Contact Information CAST, Inc. 11 Stonewall Court Woodcliff Lake, New Jersey 07677 USA Phone: +1 201-391-8300 Fax: +1 201-391-8694 E-Mail: info@cast-inc.com URL: www.cast-inc.com This megafunction developed by the processor experts at Evatronix SA Copyright (c) CAST, Inc. 2004, All Rights Reserved. Contents subject to change without notice CAST, Inc. Page 5 |
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